Networks on silicon: blessing or nightmare?

P. Wielage; K. Goossens

doi:10.1109/DSD.2002.1115369

Networks on silicon: blessing or nightmare?

P. Wielage, K. Goossens

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

58 Citations (Scopus)

Abstract

Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower and on-chip communication will be the limiting performance factor of future chips. We explain why efficiently sharing of the wires for long distance communication is the solution to this problem. We introduce networks on silicon (NoS), that route packets over shared (semi)-global wires. NoS performance is expected to be high, but comes at a cost. Balancing the performance and cost of a NoS is a major challenge, and we believe busses still have a role to play.

Original language	English
Title of host publication	Proceedings - Euromicro Symposium on Digital System Design
Subtitle of host publication	Architectures, Methods and Tools, DSD 2002
Editors	Martyn Edwards
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	196-200
Number of pages	5
ISBN (Electronic)	0-7695-1790-0
DOIs	https://doi.org/10.1109/DSD.2002.1115369
Publication status	Published - 1 Jan 2002
Externally published	Yes
Event	5th Euromicro Symposium on Digital Systems Design (DSD 2002) - Dortmund, Germany Duration: 4 Sept 2002 → 6 Sept 2002 Conference number: 5

Conference

Conference	5th Euromicro Symposium on Digital Systems Design (DSD 2002)
Abbreviated title	DSD 2002
Country/Territory	Germany
City	Dortmund
Period	4/09/02 → 6/09/02
Other	"Architectures, Methods and Tools"

Keywords

Bandwidth
Clocks
Costs
Delay effects
Laboratories
Moore's Law
Silicon
Very large scale integration
Wires
Wiring

Access to Document

10.1109/DSD.2002.1115369

Cite this

@inproceedings{ec51c1906d384779a003b6a0f563a746,

title = "Networks on silicon: blessing or nightmare?",

abstract = "Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower and on-chip communication will be the limiting performance factor of future chips. We explain why efficiently sharing of the wires for long distance communication is the solution to this problem. We introduce networks on silicon (NoS), that route packets over shared (semi)-global wires. NoS performance is expected to be high, but comes at a cost. Balancing the performance and cost of a NoS is a major challenge, and we believe busses still have a role to play.",

keywords = "Bandwidth, Clocks, Costs, Delay effects, Laboratories, Moore's Law, Silicon, Very large scale integration, Wires, Wiring",

author = "P. Wielage and K. Goossens",

year = "2002",

month = jan,

day = "1",

doi = "10.1109/DSD.2002.1115369",

language = "English",

pages = "196--200",

editor = "Martyn Edwards",

booktitle = "Proceedings - Euromicro Symposium on Digital System Design",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "5th Euromicro Symposium on Digital Systems Design (DSD 2002), DSD 2002 ; Conference date: 04-09-2002 Through 06-09-2002",

}

Wielage, P & Goossens, K 2002, Networks on silicon: blessing or nightmare? in M Edwards (ed.), Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002., 1115369, Institute of Electrical and Electronics Engineers, Piscataway, pp. 196-200, 5th Euromicro Symposium on Digital Systems Design (DSD 2002), Dortmund, Germany, 4/09/02. https://doi.org/10.1109/DSD.2002.1115369

Networks on silicon: blessing or nightmare? / Wielage, P.; Goossens, K.
Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. ed. / Martyn Edwards. Piscataway: Institute of Electrical and Electronics Engineers, 2002. p. 196-200 1115369.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Networks on silicon

T2 - 5th Euromicro Symposium on Digital Systems Design (DSD 2002)

AU - Wielage, P.

AU - Goossens, K.

N1 - Conference code: 5

PY - 2002/1/1

Y1 - 2002/1/1

N2 - Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower and on-chip communication will be the limiting performance factor of future chips. We explain why efficiently sharing of the wires for long distance communication is the solution to this problem. We introduce networks on silicon (NoS), that route packets over shared (semi)-global wires. NoS performance is expected to be high, but comes at a cost. Balancing the performance and cost of a NoS is a major challenge, and we believe busses still have a role to play.

AB - Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower and on-chip communication will be the limiting performance factor of future chips. We explain why efficiently sharing of the wires for long distance communication is the solution to this problem. We introduce networks on silicon (NoS), that route packets over shared (semi)-global wires. NoS performance is expected to be high, but comes at a cost. Balancing the performance and cost of a NoS is a major challenge, and we believe busses still have a role to play.

KW - Bandwidth

KW - Clocks

KW - Costs

KW - Delay effects

KW - Laboratories

KW - Moore's Law

KW - Silicon

KW - Very large scale integration

KW - Wires

KW - Wiring

UR - http://www.scopus.com/inward/record.url?scp=84949672053&partnerID=8YFLogxK

U2 - 10.1109/DSD.2002.1115369

DO - 10.1109/DSD.2002.1115369

M3 - Conference contribution

AN - SCOPUS:84949672053

SP - 196

EP - 200

BT - Proceedings - Euromicro Symposium on Digital System Design

A2 - Edwards, Martyn

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

Y2 - 4 September 2002 through 6 September 2002

ER -

Networks on silicon: blessing or nightmare?

Abstract

Conference

Keywords

Access to Document

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Cite this