Abstract
The cost of moving data between the memory/storage units and the compute units is a major contributor to the execution time and energy consumption of modern workloads in computing systems. A promising paradigm to alleviate this data movement bottleneck is near-memory computing (NMC), which consists of placing compute units close to the memory/storage units. There is substantial research effort that proposesNMCarchitectures and identifiesworkloads that can benefit from NMC. System architects typically use simulation techniques to evaluate the performance and energy consumption of their designs. However, simulation is extremely slow, imposing long times for design space exploration. In order to enable fast early-stage design space exploration of NMC architectures, we need high-level performance and energy models. We present NAPEL, a high-level performance and energy estimation framework for NMC architectures. NAPEL leverages ensemble learning to develop a model that is based on microarchitectural parameters and application characteristics. NAPEL training uses a statistical technique, called design of experiments, to collect representative training data efficiently. NAPEL provides early design space exploration 220× faster than a state-of-the-artNMCsimulator, on average, with error rates of to 8.5% and 11.6% for performance and energy estimations, respectively, compared to the NMC simulator. NAPEL is also capable of making accurate predictions for previously-unseen applications.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019 |
| Publisher | Institute of Electrical and Electronics Engineers |
| Number of pages | 6 |
| ISBN (Electronic) | 9781450367257 |
| DOIs | |
| Publication status | Published - 2 Jun 2019 |
| Event | 56th Annual Design Automation Conference, (DAC2019) - Las Vegas, United States Duration: 2 Jun 2019 → 6 Jun 2019 https://dac.com/ |
Conference
| Conference | 56th Annual Design Automation Conference, (DAC2019) |
|---|---|
| Abbreviated title | DAC2019 |
| Country | United States |
| City | Las Vegas |
| Period | 2/06/19 → 6/06/19 |
| Internet address |
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NAPEL : Near-memory computing application performance prediction via ensemble learning. / Singh, Gagandeep; Gómez-Luna, Juan; Mariani, Giovanni; Oliveira, Geraldo F.; Corda, Stefano; Stuijk, Sander; Mutlu, Onur; Corporaal, Henk.
Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers, 2019. a27.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - NAPEL
T2 - Near-memory computing application performance prediction via ensemble learning
AU - Singh, Gagandeep
AU - Gómez-Luna, Juan
AU - Mariani, Giovanni
AU - Oliveira, Geraldo F.
AU - Corda, Stefano
AU - Stuijk, Sander
AU - Mutlu, Onur
AU - Corporaal, Henk
PY - 2019/6/2
Y1 - 2019/6/2
N2 - The cost of moving data between the memory/storage units and the compute units is a major contributor to the execution time and energy consumption of modern workloads in computing systems. A promising paradigm to alleviate this data movement bottleneck is near-memory computing (NMC), which consists of placing compute units close to the memory/storage units. There is substantial research effort that proposesNMCarchitectures and identifiesworkloads that can benefit from NMC. System architects typically use simulation techniques to evaluate the performance and energy consumption of their designs. However, simulation is extremely slow, imposing long times for design space exploration. In order to enable fast early-stage design space exploration of NMC architectures, we need high-level performance and energy models. We present NAPEL, a high-level performance and energy estimation framework for NMC architectures. NAPEL leverages ensemble learning to develop a model that is based on microarchitectural parameters and application characteristics. NAPEL training uses a statistical technique, called design of experiments, to collect representative training data efficiently. NAPEL provides early design space exploration 220× faster than a state-of-the-artNMCsimulator, on average, with error rates of to 8.5% and 11.6% for performance and energy estimations, respectively, compared to the NMC simulator. NAPEL is also capable of making accurate predictions for previously-unseen applications.
AB - The cost of moving data between the memory/storage units and the compute units is a major contributor to the execution time and energy consumption of modern workloads in computing systems. A promising paradigm to alleviate this data movement bottleneck is near-memory computing (NMC), which consists of placing compute units close to the memory/storage units. There is substantial research effort that proposesNMCarchitectures and identifiesworkloads that can benefit from NMC. System architects typically use simulation techniques to evaluate the performance and energy consumption of their designs. However, simulation is extremely slow, imposing long times for design space exploration. In order to enable fast early-stage design space exploration of NMC architectures, we need high-level performance and energy models. We present NAPEL, a high-level performance and energy estimation framework for NMC architectures. NAPEL leverages ensemble learning to develop a model that is based on microarchitectural parameters and application characteristics. NAPEL training uses a statistical technique, called design of experiments, to collect representative training data efficiently. NAPEL provides early design space exploration 220× faster than a state-of-the-artNMCsimulator, on average, with error rates of to 8.5% and 11.6% for performance and energy estimations, respectively, compared to the NMC simulator. NAPEL is also capable of making accurate predictions for previously-unseen applications.
UR - http://www.scopus.com/inward/record.url?scp=85067833914&partnerID=8YFLogxK
U2 - 10.1145/3316781.3317867
DO - 10.1145/3316781.3317867
M3 - Conference contribution
AN - SCOPUS:85067833914
BT - Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
PB - Institute of Electrical and Electronics Engineers
ER -