Multi-processor system-level synthesis for multiple applications on platform FPGA

A. Kumar, S.D. Fernando, Y. Ha, B. Mesman, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

11 Citations (Scopus)
82 Downloads (Pure)

Abstract

Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and programming such systems prove to be a major challenge. Most of the current design methodologies rely on creating the design by hand, and are therefore error-prone and time-consuming. This also limits the number of design points that can be explored. While some efforts have been made to automate the flow and raise the abstraction level, these are still limited to single-application designs. In this paper, we present a design methodology to generate and program MPSoC designs in a systematic and automated way for multiple applications. The architecture is automatically inferred from the application specifications, and customized for it. The flow is ideal for fast design space exploration (DSE) in MPSoC systems. We present results of a case study to compute the buffer-throughput trade-offs in real-life applications, H263 and JPEG decoders. The generation of the entire project takes about 100 ms, and the whole DSE was completed in 45 minutes, including the FPGA mapping and synthesis.
Original languageEnglish
Title of host publicationInternational Conference on Field Programmable Logic and Applications, 2007 : FPL 2007 ; 27 - 29 Aug. 2007, Amsterdam, The Netherlands
EditorsKoen Bertels
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages92-97
ISBN (Print)978-1-4244-1060-6
DOIs
Publication statusPublished - 2007

Fingerprint

Dive into the research topics of 'Multi-processor system-level synthesis for multiple applications on platform FPGA'. Together they form a unique fingerprint.

Cite this