Multi-media processor architecture with high performance-density

A multimedia system has unprogrammable task-specific processors of high performance-density. The task-specific processors perform primitive functions that together constitute a video algorithm. The task-specific processors are interconnected via a high-speed communication module whose interconnectivity is controlled by an arbiter. The arbiter stores a data flow graph. A fully programmable general-purpose processor of low performance-density carries out those tasks that are not readily mapped onto the primitive functions. This configuration with different levels of performance-density and programmability increases overall system performance-density with regard to the prior art.