We present a method to design multi-dimensional rank order filters. Our designs are more efficient than existing ones from literature, e.g. reducing the number of operations required by a 2-dimensional 7 × 7 median filter by 66%. This efficiency is maintained regardless of the amount of parallelism, therefore the throughput of our designs scales linearly with the amount of hardware. To accomplish this we introduce a framework in the form of a generator graph. This graph allows us to formalize our methods and formulate an algorithm that produces efficient designs by reusing common sub-expressions. Like other rank order filters our designs are based on sorting networks composed from Batcher’s merging networks. However, we introduce an additional optimization that increases the savings obtained by pruning sorting networks. Our design method is independent of the implementation method and resulting designs can be implemented both as a VLSI circuit and as a program for an SIMD processor.
|Title of host publication||Proceedings of the 2007 IEEE Workshop on Signal Processing Systems (SiPS 2007) 17-19 October 2007, Shanghai, China|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2007|
|Event||conference; SiPS 2007; 2007-10-17; 2007-10-19 - |
Duration: 17 Oct 2007 → 19 Oct 2007
|Conference||conference; SiPS 2007; 2007-10-17; 2007-10-19|
|Period||17/10/07 → 19/10/07|