Montgomery in practice: how to do it more efficiently in hardware

L. Batina, G. Bruin - Muurling

    Research output: Chapter in Book/Report/Conference proceedingConference contributionProfessional

    17 Citations (Scopus)
    10 Downloads (Pure)


    This work describes a fully scalable hardware architecture for modular multiplication which is efficient for an arbitrary bit length. This solution uses a systolic array implementation and can be used for arbitary precision without any modification. This notion of scalability includes both, freedom in choice of operand precision as well as adaptability to any desired gate complexity. We present modular exponentiation based on Montgomery’s method without any modular reduction achieving the best possible bound according to C. Walter. Even more, this tight bound appeared to be practical in our architecture. The described systolic array architecture is unique, being scalable in several parameters and resulting in a class of exponentiation engines. The data provided in the figures and tables are believed to be new, providing a practical dimension of this work.
    Original languageEnglish
    Title of host publicationTopics in cryptology - CT-RSA 2002: the cryptographers' track at RSA conference, 2nd, San Jose, CA., USA, February 18-22 2002
    EditorsB. Preneel
    Place of PublicationBerlin
    ISBN (Print)978-3-540-43224-1
    Publication statusPublished - 2002
    Eventconference; RSA Conference -
    Duration: 1 Jan 2002 → …

    Publication series

    NameLecture Notes in Computer Science
    ISSN (Print)0302-9743


    Conferenceconference; RSA Conference
    Period1/01/02 → …
    OtherRSA Conference


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