Modeling TL task structures and interrupts in VHDL : construction of a TL to VHDL compiler

Research output: Thesis › EngD Thesis

Original language	English
Supervisors/Advisors	Benders, L.P.M., Supervisor Stevens, M.P.J., Supervisor
Award date	1 Jan 1994
Place of Publication	Eindhoven
Publisher	Eindhoven University of Technology
Print ISBNs	90-5282-374-X
Publication status	Published - 1994

Eindverslag.

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