Modeling TL task structures and interrupts in VHDL : construction of a TL to VHDL compiler

M.V. Boersma, Technische Universiteit Eindhoven (TUE). Stan Ackermans Instituut. Information and Communication Technology (ICT)

Research output: Thesis › Pd Eng Thesis

Original language	English
Qualification	Doctor of Philosophy
Awarding Institution
Supervisors/Advisors	Benders, L.P.M., Supervisor Stevens, M.P.J., Supervisor
Award date	1 Jan 1994
Place of Publication	Eindhoven
Publisher	Eindhoven University of Technology
Print ISBNs	90-5282-374-X
Publication status	Published - 1994

Eindverslag.

Cite this

@phdthesis{c629dd1f1cb74d67ab9fd24868daecaa,

title = "Modeling TL task structures and interrupts in VHDL : construction of a TL to VHDL compiler",

author = "M.V. Boersma and {Technische Universiteit Eindhoven (TUE). Stan Ackermans Instituut. Information and Communication Technology (ICT)}",

note = "Eindverslag.",

year = "1994",

language = "English",

isbn = "90-5282-374-X",

publisher = "Eindhoven University of Technology",

}

TY - THES

T1 - Modeling TL task structures and interrupts in VHDL : construction of a TL to VHDL compiler

AU - Boersma, M.V.

AU - Technische Universiteit Eindhoven (TUE). Stan Ackermans Instituut. Information and Communication Technology (ICT)

N1 - Eindverslag.

PY - 1994

Y1 - 1994

M3 - Pd Eng Thesis

SN - 90-5282-374-X

PB - Eindhoven University of Technology

CY - Eindhoven

ER -