Modeling TL task structures and interrupts in VHDL : construction of a TL to VHDL compiler

M.V. Boersma, Technische Universiteit Eindhoven (TUE). Stan Ackermans Instituut. Information and Communication Technology (ICT)

    Research output: ThesisPd Eng Thesis

    Original languageEnglish
    QualificationDoctor of Philosophy
    Awarding Institution
    Supervisors/Advisors
    • Benders, L.P.M., Supervisor
    • Stevens, M.P.J., Supervisor
    Award date1 Jan 1994
    Place of PublicationEindhoven
    Publisher
    Print ISBNs90-5282-374-X
    Publication statusPublished - 1994

    Bibliographical note

    Eindverslag.

    Cite this

    Boersma, M. V., & Technische Universiteit Eindhoven (TUE). Stan Ackermans Instituut. Information and Communication Technology (ICT) (1994). Modeling TL task structures and interrupts in VHDL : construction of a TL to VHDL compiler. Eindhoven University of Technology.