Modeling TL task structures and interrupts in VHDL : construction of a TL to VHDL compiler

M.V. Boersma, Technische Universiteit Eindhoven (TUE). Stan Ackermans Instituut. Information and Communication Technology (ICT)

    Research output: ThesisEngD Thesis

    Original languageEnglish
    QualificationDoctor of Philosophy
    Awarding Institution
    • Benders, L.P.M., Supervisor
    • Stevens, M.P.J., Supervisor
    Award date1 Jan 1994
    Place of PublicationEindhoven
    Print ISBNs90-5282-374-X
    Publication statusPublished - 1994

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