Modeling reconfiguration in a FPGA with a hardwired network on chip

M.A. Wahlah, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

We propose that FPGAs use a hardwired network on chip (HWNOC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstreams for soft IP). In this paper we model such a platform. Using the HWNOC applications mapped on hard or soft IPs are set up and removed using memory-mapped communications. Peer-to-peer streaming data is used to communicate data between IPs, and also to transport configuration bitstreams. The composable nature of the HWNOC ensures that applications can be dynamically configured, programmed, and can operate, without affecting other running (real-time) applications. We describe this platform and the steps required for dynamic reconfiguration of IPs. We then model the hardware, i.e. HWNOC and hard and soft IPs, in cycle-accurate transaction-level SystemC. Next, we model its dynamic behavior, including bitstream loading, HWNOC programming, dynamic (re)configuration, clocking, reset, and computation. © 2009 IEEE.
Original languageEnglish
Title of host publication23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009, 23 May - 29 May 2009, Rome
DOIs
Publication statusPublished - 2009

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    Wahlah, M. A., & Goossens, K. G. W. (2009). Modeling reconfiguration in a FPGA with a hardwired network on chip. In 23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009, 23 May - 29 May 2009, Rome https://doi.org/10.1109/IPDPS.2009.5161213