Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

Shayesteh Masoumian; Roel Maes; Rui Wang; Karthik Keni Yerriswamy; Geert Jan Schrijen; Said Hamdioui; Mottaqiallah Taouil

doi:10.1109/VLSI-SOC57769.2023.10321895

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

Shayesteh Masoumian
, Roel Maes
, Rui Wang
, Karthik Keni Yerriswamy
, Geert Jan Schrijen
, Said Hamdioui
, Mottaqiallah Taouil

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.

Original language	English
Title of host publication	2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	6
ISBN (Electronic)	979-8-3503-2599-7
DOIs	https://doi.org/10.1109/VLSI-SOC57769.2023.10321895
Publication status	Published - 22 Nov 2023
Externally published	Yes
Event	31st International Conference on Very Large Scale Integration, VLSI-SoC 2023 - Dubai, United Arab Emirates Duration: 16 Oct 2023 → 18 Oct 2023

Conference

Conference	31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
Abbreviated title	VLSI-SoC 2023
Country/Territory	United Arab Emirates
City	Dubai
Period	16/10/23 → 18/10/23

Funding

This work is partially funded by the Resilient Trust project of the EU s Horizon Europe research and innovation programme under grant agreement No. 101112282.

Funders	Funder number
European Union's Horizon 2020 - Research and Innovation Framework Programme	101112282

Keywords

Bias
FinFET
Power Supply Network
SRAM PUF
Temperature

Access to Document

10.1109/VLSI-SOC57769.2023.10321895

Cite this

Masoumian, S., Maes, R., Wang, R., Yerriswamy, K. K., Schrijen, G. J., Hamdioui, S., & Taouil, M. (2023). Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. In 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023 Article 10321895 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSI-SOC57769.2023.10321895

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title = "Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes",

abstract = "SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.",

keywords = "Bias, FinFET, Power Supply Network, SRAM PUF, Temperature",

author = "Shayesteh Masoumian and Roel Maes and Rui Wang and Yerriswamy, \{Karthik Keni\} and Schrijen, \{Geert Jan\} and Said Hamdioui and Mottaqiallah Taouil",

year = "2023",

month = nov,

day = "22",

doi = "10.1109/VLSI-SOC57769.2023.10321895",

language = "English",

booktitle = "2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023",

publisher = "Institute of Electrical and Electronics Engineers",

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Masoumian, S, Maes, R, Wang, R, Yerriswamy, KK, Schrijen, GJ, Hamdioui, S & Taouil, M 2023, Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023., 10321895, Institute of Electrical and Electronics Engineers, 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, 16/10/23. https://doi.org/10.1109/VLSI-SOC57769.2023.10321895

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. / Masoumian, Shayesteh; Maes, Roel; Wang, Rui et al.
2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. Institute of Electrical and Electronics Engineers, 2023. 10321895.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

AU - Masoumian, Shayesteh

AU - Maes, Roel

AU - Wang, Rui

AU - Yerriswamy, Karthik Keni

AU - Schrijen, Geert Jan

AU - Hamdioui, Said

AU - Taouil, Mottaqiallah

PY - 2023/11/22

Y1 - 2023/11/22

N2 - SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.

AB - SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.

KW - Bias

KW - FinFET

KW - Power Supply Network

KW - SRAM PUF

KW - Temperature

UR - https://www.scopus.com/pages/publications/85179842026

U2 - 10.1109/VLSI-SOC57769.2023.10321895

DO - 10.1109/VLSI-SOC57769.2023.10321895

M3 - Conference contribution

BT - 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023

PB - Institute of Electrical and Electronics Engineers

T2 - 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023

Y2 - 16 October 2023 through 18 October 2023

ER -

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

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