Modeling and analysis of FPGA accelerators for real-time streaming video processing in the healthcare domain

Steven van der Vlugt (Corresponding author), Hadi Alizadeh Ara, Rob de Jong, Martijn Hendriks, Ruben Guerra Marin, Marc Geilen, Dip Goswami

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Abstract

Complex real-time video processing applications with strict throughput constraints are commonly found in a typical healthcare application. The video processing chain is implemented as Field-Programmable Gate Array (FPGA) accelerators (processing blocks) communicating through a number of First-In First-Out (FIFO) buffers. The FIFO buffers are made out of Block RAM (BRAM) and limited in availability. Therefore, a key design question is the optimal sizes of the FIFO buffers with respect to the throughput constraint. In this paper, we use model-driven analysis and detailed hardware level simulation to address the question of buffer dimensioning in an efficient way. Using a Cyclo-Static Dataflow (CSDF) model and an optimization method, we identify and optimize the FIFO buffers. The results are confirmed using a detailed hardware level simulation and validated by comparison with VHDL simulations. The technique is illustrated on a use case from Philips Healthcare Image Guided Therapy (IGT) on the imaging pipeline of an Interventional X-Ray (i XR) system.

Original languageEnglish
Pages (from-to)75-91
Number of pages17
JournalJournal of Signal Processing Systems
Volume91
Issue number1
DOIs
Publication statusPublished - 1 Jan 2019

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Keywords

  • Buffer sizing
  • Latency
  • Optimized hardware synthesis
  • Throughput

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