Model-based processor-in-the-loop framework for composable multi-core platforms

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From model-based design to implementation on an embedded platform requires target-specific code generation, compilation, and execution. Processor-in-the-loop (PIL) simulation is an intermediate step meant for detailed testing and debugging in the development process. This paper presents a PIL simulation framework targeting multi-core FPGA-based embedded platforms. The presented framework allows for a fully automated process of performing PIL simulations on an FPGA-based embedded platform - CompSOC - starting from a Simulink model. The framework includes two PIL configurations - one configuration executes only the controller code on the target platform while other configuration executes both the controller and the plant code on the target platform. It considers scheduling of multiple applications and interference-free execution on the target platform under the PIL configurations. Further, the framework allows for logging various measurements of parameters such as execution time, memory usage and so on in the PIL configurations which can be used for testing and debugging purposes.

Original languageEnglish
Title of host publicationProceedings - Euromicro Conference on Digital System Design, DSD 2019
EditorsNikos Konofaos, Paris Kitsos
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages5
ISBN (Electronic)9781728128610
Publication statusPublished - Aug 2019
Event22nd Euromicro Conference on Digital System Design, DSD 2019 - Kallithea, Kallithea, Chalkidiki, Greece
Duration: 28 Aug 201930 Aug 2019
Conference number: 22


Conference22nd Euromicro Conference on Digital System Design, DSD 2019
Abbreviated titleDSD 2019
CityKallithea, Chalkidiki
Internet address


  • Embedded control
  • Model-based simulation
  • PIL simulation


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