Abstract
From model-based design to implementation on an embedded platform requires target-specific code generation, compilation, and execution. Processor-in-the-loop (PIL) simulation is an intermediate step meant for detailed testing and debugging in the development process. This paper presents a PIL simulation framework targeting multi-core FPGA-based embedded platforms. The presented framework allows for a fully automated process of performing PIL simulations on an FPGA-based embedded platform - CompSOC - starting from a Simulink model. The framework includes two PIL configurations - one configuration executes only the controller code on the target platform while other configuration executes both the controller and the plant code on the target platform. It considers scheduling of multiple applications and interference-free execution on the target platform under the PIL configurations. Further, the framework allows for logging various measurements of parameters such as execution time, memory usage and so on in the PIL configurations which can be used for testing and debugging purposes.
Original language | English |
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Title of host publication | Proceedings - Euromicro Conference on Digital System Design, DSD 2019 |
Editors | Nikos Konofaos, Paris Kitsos |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 592-596 |
Number of pages | 5 |
ISBN (Electronic) | 9781728128610 |
DOIs | |
Publication status | Published - Aug 2019 |
Event | 22nd Euromicro Conference on Digital System Design, DSD 2019 - Kallithea, Kallithea, Chalkidiki, Greece Duration: 28 Aug 2019 → 30 Aug 2019 Conference number: 22 http://dsd-seaa2019.csd.auth.gr/ |
Conference
Conference | 22nd Euromicro Conference on Digital System Design, DSD 2019 |
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Abbreviated title | DSD 2019 |
Country/Territory | Greece |
City | Kallithea, Chalkidiki |
Period | 28/08/19 → 30/08/19 |
Internet address |
Keywords
- Embedded control
- Model-based simulation
- PIL simulation