Mixed-Length SIMD Code Generation for VLIW Architectures with Multiple Native Vector-Widths

E. Diken, M. O'Riordan, R. Jordans, L. Jozwiak, H. Corporaal, D. Moloney

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)
3 Downloads (Pure)


The degree of DLP parallelism in applications is not fixed and varies due to different computational characteristics of applications. On the contrary, most of the processors today include single-width SIMD (vector) hardware to exploit DLP. However, single-width SIMD architectures may not be optimal to serve applications with varying DLP and they may cause performance and energy inefficiency. We propose the usage of VLIW processors with multiple native vector-widths to better serve applications with changing DLP. SHAVE is an example of such VLIW processor and provides hardware support for the native 32-bit and 128-bit wide vector operations. This paper researches and implements the mixed-length SIMD code generation support for SHAVE processor. More specifically, we target generating 32-bit and 128/64-bit SIMD code for the native 32-bit and 128-bit wide vector units of SHAVE processor. In this way, we improved the performance of compiler generated SIMD code by reducing the number of overhead operations and by increasing the SIMD hardware utilization. Experimental results demonstrated that our methodology implemented in the compiler improves the performance of synthetic benchmarks up to 47%.
Original languageEnglish
Title of host publicationASAP 2015 - 26th IEEE International Conference on Application-specific Systems, Architectures and Processors, 27-29 July 2015, Toronto, Canada
Place of PublicationToronto, Canada
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2015
Eventconference; ASAP; 2015-07-27; 2015-07-29 -
Duration: 27 Jul 201529 Jul 2015


Conferenceconference; ASAP; 2015-07-27; 2015-07-29


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