Mismatch-Based Timing Errors in Current Steering DACs

K. Doris; A.H.M. Roermund, van; D.M.W. Leenaerts

doi:10.1109/ISCAS.2003.1205729

Mismatch-Based Timing Errors in Current Steering DACs

K. Doris, A.H.M. Roermund, van, D.M.W. Leenaerts

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

23 Citations (Scopus)

Abstract

Current Steering Digital-to-Analog Converters (CS-DAC) are important ingredients in many high-speed data converters. Various types of timing errors such as mismatch based timing errors limit broad-band performance. A framework of timing errors is presented here and it is used to analyze these errors. The extracted relationship between performance, block requirements and architecture (e.g segmentation) gives insight on design tradeoffs in Nyquist DACs and multi-bit current-based /spl Sigma//spl Delta/ Modulators.

Original language	English
Title of host publication	2003 International Symposium on Circuits and Systems, 2003. ISCAS '03
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	977-980
Volume	1
ISBN (Print)	0-7803-7761-3
DOIs	https://doi.org/10.1109/ISCAS.2003.1205729
Publication status	Published - 2003

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10.1109/ISCAS.2003.1205729

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title = "Mismatch-Based Timing Errors in Current Steering DACs",

abstract = "Current Steering Digital-to-Analog Converters (CS-DAC) are important ingredients in many high-speed data converters. Various types of timing errors such as mismatch based timing errors limit broad-band performance. A framework of timing errors is presented here and it is used to analyze these errors. The extracted relationship between performance, block requirements and architecture (e.g segmentation) gives insight on design tradeoffs in Nyquist DACs and multi-bit current-based /spl Sigma//spl Delta/ Modulators.",

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Mismatch-Based Timing Errors in Current Steering DACs. / Doris, K.; Roermund, van, A.H.M.; Leenaerts, D.M.W.

2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. Vol. 1 Piscataway : Institute of Electrical and Electronics Engineers, 2003. p. 977-980.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Mismatch-Based Timing Errors in Current Steering DACs

AU - Doris, K.

AU - Roermund, van, A.H.M.

AU - Leenaerts, D.M.W.

PY - 2003

Y1 - 2003

N2 - Current Steering Digital-to-Analog Converters (CS-DAC) are important ingredients in many high-speed data converters. Various types of timing errors such as mismatch based timing errors limit broad-band performance. A framework of timing errors is presented here and it is used to analyze these errors. The extracted relationship between performance, block requirements and architecture (e.g segmentation) gives insight on design tradeoffs in Nyquist DACs and multi-bit current-based /spl Sigma//spl Delta/ Modulators.

AB - Current Steering Digital-to-Analog Converters (CS-DAC) are important ingredients in many high-speed data converters. Various types of timing errors such as mismatch based timing errors limit broad-band performance. A framework of timing errors is presented here and it is used to analyze these errors. The extracted relationship between performance, block requirements and architecture (e.g segmentation) gives insight on design tradeoffs in Nyquist DACs and multi-bit current-based /spl Sigma//spl Delta/ Modulators.

U2 - 10.1109/ISCAS.2003.1205729

DO - 10.1109/ISCAS.2003.1205729

M3 - Conference contribution

SN - 0-7803-7761-3

VL - 1

SP - 977

EP - 980

BT - 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Mismatch-Based Timing Errors in Current Steering DACs

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