Minimizing pattern count for interconnect test under a ground bounce constraint

E.J. Marinissen; B. Vermeulen; H. Hollmann; R.G. Bennetts

doi:10.1109/MDT.2003.1188257

Minimizing pattern count for interconnect test under a ground bounce constraint

E.J. Marinissen, B. Vermeulen, H. Hollmann, R.G. Bennetts

Research output: Contribution to journal › Article › Academic › peer-review

19 Citations (Scopus)

Abstract

When testing the interconnect structures on a board, test programmers sometimes ask, How can I control the test pattern generation process to avoid ground bounce problems during Extest mode? Those wishing to satisfy a simultaneously-switching-outputs constraint will find several new solutions in this article.

Original language	English
Pages (from-to)	8-18
Journal	IEEE Design and Test of Computers
Volume	20
Issue number	2
DOIs	https://doi.org/10.1109/MDT.2003.1188257
Publication status	Published - 2003
Externally published	Yes

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title = "Minimizing pattern count for interconnect test under a ground bounce constraint",

abstract = "When testing the interconnect structures on a board, test programmers sometimes ask, How can I control the test pattern generation process to avoid ground bounce problems during Extest mode? Those wishing to satisfy a simultaneously-switching-outputs constraint will find several new solutions in this article.",

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Minimizing pattern count for interconnect test under a ground bounce constraint

Abstract

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