Methodology for building processor design space exploration frameworks.

F. Barat, T. Aa, van der, M. Jayapala, G. Deconinck, R. Lauwereins, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Original languageEnglish
Title of host publicationProceedings of 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005)
Publication statusPublished - 2005
Event3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005) - San Jose, CA, United States
Duration: 20 Mar 200523 Mar 2005
Conference number: 3

Workshop

Workshop3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005)
Abbreviated titleODES 2005
Country/TerritoryUnited States
CitySan Jose, CA
Period20/03/0523/03/05

Cite this