Methodology for building processor design space exploration frameworks.

F. Barat, T. Aa, van der, M. Jayapala, G. Deconinck, R. Lauwereins, H. Corporaal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Proceedings of 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005)
Publication status	Published - 2005
Event	3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005) - San Jose, United States Duration: 20 Mar 2005 → 23 Mar 2005 Conference number: 3

Workshop	3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005)
Abbreviated title	ODES 2005
Country/Territory	United States
City	San Jose
Period	20/03/05 → 23/03/05

Cite this

@inproceedings{be1f3a925e2e4568a253bbe9e42543f6,

title = "Methodology for building processor design space exploration frameworks.",

author = "F. Barat and {Aa, van der}, T. and M. Jayapala and G. Deconinck and R. Lauwereins and H. Corporaal",

year = "2005",

language = "English",

booktitle = "Proceedings of 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005)",

note = "3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005), ODES 2005 ; Conference date: 20-03-2005 Through 23-03-2005",

}

TY - GEN

T1 - Methodology for building processor design space exploration frameworks.

AU - Barat, F.

AU - Aa, van der, T.

AU - Jayapala, M.

AU - Deconinck, G.

AU - Lauwereins, R.

AU - Corporaal, H.

N1 - Conference code: 3

PY - 2005

Y1 - 2005

M3 - Conference contribution

BT - Proceedings of 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005)

T2 - 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005)

Y2 - 20 March 2005 through 23 March 2005

ER -