Method of plating through wafer vias in a wafer for 3d packaging

W.F.A. Besling (Inventor), F. Roozeboom (Inventor), Y. Lamy (Inventor)

Research output: PatentPatent publication

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Abstract

A method of plating via hole in a substrate includes providing a substrate having a first side and a second side and a plurality of through substrate via holes; depositing a first seed layer on the first side of the substrate; applying a foil on the first seed layer of the substrate closing the first ends of the plurality of via holes; electro-chemical plating of the second side of the substrate; and removing the foil
Original languageEnglish
Patent numberUS8455357
Publication statusPublished - 4 Jun 2013
Externally publishedYes

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  • Cite this

    Besling, W. F. A., Roozeboom, F., & Lamy, Y. (2013). Method of plating through wafer vias in a wafer for 3d packaging. (Patent No. US8455357).