Method of plating through wafer vias in a wafer for 3d packaging

W.F.A. Besling; F. Roozeboom; Y. Lamy

Method of plating through wafer vias in a wafer for 3d packaging

W.F.A. Besling (Inventor), F. Roozeboom (Inventor), Y. Lamy (Inventor)

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Abstract

Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.

Original language	English
Patent number	WO2010041165
Publication status	Published - 15 Apr 2010

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title = "Method of plating through wafer vias in a wafer for 3d packaging",

abstract = "Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.",

author = "W.F.A. Besling and F. Roozeboom and Y. Lamy",

year = "2010",

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day = "15",

language = "English",

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T1 - Method of plating through wafer vias in a wafer for 3d packaging

AU - Besling, W.F.A.

AU - Roozeboom, F.

AU - Lamy, Y.

PY - 2010/4/15

Y1 - 2010/4/15

N2 - Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.

AB - Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.

UR - http://v3.espacenet.com/publicationDetails/biblio?DB=EPODOC&adjacent=true&locale=nl_nl&FT=D&date=20100415&CC=WO&NR=2010041165A1&KC=A1

M3 - Patent publication

M1 - WO2010041165

ER -

Method of plating through wafer vias in a wafer for 3d packaging

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