Method of plating through wafer vias in a wafer for 3d packaging

W.F.A. Besling (Inventor), F. Roozeboom (Inventor), Y. Lamy (Inventor)

    Research output: PatentPatent publication

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    Abstract

    Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.
    Original languageEnglish
    Patent numberWO2010041165
    Publication statusPublished - 15 Apr 2010

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  • Cite this

    Besling, W. F. A., Roozeboom, F., & Lamy, Y. (2010). Method of plating through wafer vias in a wafer for 3d packaging. (Patent No. WO2010041165).