Method of manufacturing a capacitor on a nanowire and integrated circuit having such a capacitor

J.T.M. van Beek (Inventor), E.P.A.M. Bakkers (Inventor), F. Roozeboom (Inventor)

Research output: PatentPatent publication

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Abstract

A method of manufacturing a capacitor on a wafer, and an IC comprising such a capacitor is disclosed. The method comprises forming a plurality of vertical structures (140) each having a sub-micron thickness on the wafer; and growing a metal-insulator-metal (MIM) stack (150) over the plurality of vertical structures (140). In a preferred embodiment, the method further comprises depositing a catalyst layer (130) over the wafer; and patterning the catalyst layer, and wherein the step of forming the plurality of vertical structures (140) comprises growing a plurality of nanowires on the patterned catalyst layer. Consequently, a capacitor formed by the MIM stack (150) is obtained that has a very high capacitance density and that can be formed on top of an IC in the back- end process of an IC manufacturing process.
Original languageEnglish
Patent numberWO2009133510
Publication statusPublished - 5 Nov 2009

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