The method for modifying a representation of a digital circuit (102) in order to allow a scan test comprises a step (106) for selecting a number of the memory elements of the circuit to be made scannable. In this step it is determined whether the circuit comprises a redundant structure. In case of a sequentially redundant structure (200), a memory element (214,216,218,220) of this structure is selected to be made scannable thus providing a pseudo input to the structure and removing the redundancy during scan test. In case of a combinational redundant structure (406), a memory element (404) connecting this structure to another part of the circuit is selected to be made scannable, thus avoiding the propagation of the redundancy of the structure.
|IPC||G01R 31/ 3185 A I|
|Publication status||Published - 11 Dec 2001|