Method for improving writability of SRAM memory

V. Sharma; S. Cosemans; W. Dehaene; F. Catthoor; M. Ashouei; J. Huisken

Method for improving writability of SRAM memory

V. Sharma (Inventor), S. Cosemans (Inventor), W. Dehaene (Inventor), F. Catthoor (Inventor), M. Ashouei (Inventor), J. Huisken (Inventor)

Research output: Patent › Patent publication

Abstract

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Original language	English
Patent number	US2012063211
IPC	G11C 11/ 00 A I
Priority date	13/09/11
Publication status	Published - 15 Mar 2012
Externally published	Yes

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title = "Method for improving writability of SRAM memory",

abstract = "A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.",

author = "V. Sharma and S. Cosemans and W. Dehaene and F. Catthoor and M. Ashouei and J. Huisken",

year = "2012",

month = mar,

day = "15",

language = "English",

type = "Patent",

note = "US2012063211; G11C 11/ 00 A I",

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TY - PAT

T1 - Method for improving writability of SRAM memory

AU - Sharma, V.

AU - Cosemans, S.

AU - Dehaene, W.

AU - Catthoor, F.

AU - Ashouei, M.

AU - Huisken, J.

PY - 2012/3/15

Y1 - 2012/3/15

N2 - A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

AB - A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

M3 - Patent publication

M1 - US2012063211

ER -

Method for improving writability of SRAM memory

Abstract

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