Method and device for testing TSVs in a 3D chip stack

G. van der Plas (Inventor), E.J. Marinissen (Inventor), N. Minas (Inventor), P. Marchal (Inventor)

Research output: PatentPatent publication

Abstract

A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.

Original languageEnglish
Patent numberUS2011102011
IPCH01L 23/ 528 A I
Priority date27/09/10
Publication statusPublished - 5 May 2011
Externally publishedYes

Cite this