Method and device for testing a phase locked loop.

J. Pineda de Gyvez (Inventor), A.G. Gronthoud (Inventor), C. Cenci (Inventor)

Research output: PatentPatent publication


According to an example embodiment, there is a testing device for testing a phase locked loop having a power supply input. The testing device comprises a power supply unit for providing a power supply signal VDD having a variation profile to the power supply input of the phase locked loop, wherein a width and height of said variation profile are formed in such a way, that the voltage controlled oscillator is prevented from outputting an oscillating output signal. There is a means for disabling a feedback signal to a phase comparator of the phase locked loop such that said phase locked loop is operated in an open loop mode, and a meter for measuring a measurement signal of the phase locked loop, while said power supply signal is provided to the power supply input.
Original languageEnglish
Patent numberUS7477110
Publication statusPublished - 13 Jan 2009


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