MeSAP: a fast analytic power model for DRAM memories

S. Poddar, R. Jongerius, L. Fiorin, G. Mariani, G. Dittmann, A. Anghel, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

The design of an energy-efficient memory subsystem is one of the key issues that system architects face today. To achieve this goal, architects usually rely on system simulators and trace-based DRAM power models. However, their long execution time makes the approach infeasible for the design-space exploration of next-generation exascale computing systems. Analytic models, in contrast, are orders of magnitude faster. In this paper, we propose a new analytic memory-scheduler-agnostic power model for DRAM, henceforth referred to as MeSAP. Similarly to state-of-the-art trace-based approaches, our analytic model achieves an average error of 20%, while being an order of magnitude faster. Furthermore, we integrate MeSAP into an analytic performance model of general-purpose processors and show its applicability to the design of a computing system targeting scientific image processing applications.

Original languageEnglish
Title of host publicationProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages49-54
Number of pages6
ISBN (Electronic)978-3-9815-3709-3
DOIs
Publication statusPublished - 11 May 2017
Event20th Design, Automation and Test in Europe Conference (DATE 2017) - Swisstech, Lausanne, Switzerland
Duration: 27 Mar 201731 Mar 2017
Conference number: 20
https://www.date-conference.com/date17/

Conference

Conference20th Design, Automation and Test in Europe Conference (DATE 2017)
Abbreviated titleDATE 2017
CountrySwitzerland
CityLausanne
Period27/03/1731/03/17
Internet address

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