Abstract
This work proposes solutions for bounding the worst-case memory space requirement for parallel tasks running on multicore platforms with scratchpad memories. It introduces a feasibility test that verifies whether memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. It is shown how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analysis techniques on synthetic workload and state-of-the-art benchmarks.
Original language | English |
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Title of host publication | Proceedings - 39th IEEE Real-Time Systems Symposium, RTSS 2018 |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 312-324 |
Number of pages | 13 |
ISBN (Electronic) | 9781538679074 |
DOIs | |
Publication status | Published - 7 Jan 2019 |
Externally published | Yes |
Event | 39th IEEE Real-Time Systems Symposium, RTSS 2018 - Nashville, United States Duration: 11 Dec 2018 → 14 Dec 2018 |
Conference
Conference | 39th IEEE Real-Time Systems Symposium, RTSS 2018 |
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Country/Territory | United States |
City | Nashville |
Period | 11/12/18 → 14/12/18 |
Funding
This work has been partially supported by the RETINA Eurostars Project E10171 and by National Funds through FCT (Portuguese Foundation for Science and Technology) within the CISTER Research Unit (CEC/04234).
Keywords
- memory feasibility
- parallel tasks
- real-time
- scratchpad memories