Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures

Daniel Casini; Alessandro Biondi; Geoffrey Nelissen; Giorgio Buttazzo

doi:10.1109/RTSS.2018.00047

Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures

Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, Giorgio Buttazzo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

15 Citations (Scopus)

Abstract

This work proposes solutions for bounding the worst-case memory space requirement for parallel tasks running on multicore platforms with scratchpad memories. It introduces a feasibility test that verifies whether memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. It is shown how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analysis techniques on synthetic workload and state-of-the-art benchmarks.

Original language	English
Title of host publication	Proceedings - 39th IEEE Real-Time Systems Symposium, RTSS 2018
Publisher	Institute of Electrical and Electronics Engineers
Pages	312-324
Number of pages	13
ISBN (Electronic)	9781538679074
DOIs	https://doi.org/10.1109/RTSS.2018.00047
Publication status	Published - 7 Jan 2019
Externally published	Yes
Event	39th IEEE Real-Time Systems Symposium, RTSS 2018 - Nashville, United States Duration: 11 Dec 2018 → 14 Dec 2018

Conference

Conference	39th IEEE Real-Time Systems Symposium, RTSS 2018
Country/Territory	United States
City	Nashville
Period	11/12/18 → 14/12/18

Funding

This work has been partially supported by the RETINA Eurostars Project E10171 and by National Funds through FCT (Portuguese Foundation for Science and Technology) within the CISTER Research Unit (CEC/04234).

Keywords

memory feasibility
parallel tasks
real-time
scratchpad memories

Access to Document

10.1109/RTSS.2018.00047

Cite this

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title = "Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures",

abstract = "This work proposes solutions for bounding the worst-case memory space requirement for parallel tasks running on multicore platforms with scratchpad memories. It introduces a feasibility test that verifies whether memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. It is shown how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analysis techniques on synthetic workload and state-of-the-art benchmarks.",

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author = "Daniel Casini and Alessandro Biondi and Geoffrey Nelissen and Giorgio Buttazzo",

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doi = "10.1109/RTSS.2018.00047",

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Casini, D, Biondi, A, Nelissen, G & Buttazzo, G 2019, Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures. in Proceedings - 39th IEEE Real-Time Systems Symposium, RTSS 2018., 8603223, Institute of Electrical and Electronics Engineers, pp. 312-324, 39th IEEE Real-Time Systems Symposium, RTSS 2018, Nashville, United States, 11/12/18. https://doi.org/10.1109/RTSS.2018.00047

Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures. / Casini, Daniel; Biondi, Alessandro; Nelissen, Geoffrey et al.
Proceedings - 39th IEEE Real-Time Systems Symposium, RTSS 2018. Institute of Electrical and Electronics Engineers, 2019. p. 312-324 8603223.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures

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AU - Biondi, Alessandro

AU - Nelissen, Geoffrey

AU - Buttazzo, Giorgio

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N2 - This work proposes solutions for bounding the worst-case memory space requirement for parallel tasks running on multicore platforms with scratchpad memories. It introduces a feasibility test that verifies whether memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. It is shown how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analysis techniques on synthetic workload and state-of-the-art benchmarks.

AB - This work proposes solutions for bounding the worst-case memory space requirement for parallel tasks running on multicore platforms with scratchpad memories. It introduces a feasibility test that verifies whether memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. It is shown how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analysis techniques on synthetic workload and state-of-the-art benchmarks.

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BT - Proceedings - 39th IEEE Real-Time Systems Symposium, RTSS 2018

PB - Institute of Electrical and Electronics Engineers

T2 - 39th IEEE Real-Time Systems Symposium, RTSS 2018

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ER -

Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures

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Keywords

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