Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends

K.B. Akesson, Po-Chun Huang, F. Clermidy, D. Dutoit, K.G.W. Goossens, Yuan-Hao Chang, Tei-Wei Kuo, P. Vivet, D. Wingard

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

14 Citations (Scopus)

Abstract

Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power.
Original languageEnglish
Title of host publicationProceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages3-12
ISBN (Print)978-1-4503-0715-4
Publication statusPublished - 2011
Event2011 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011) - Taipe, Taiwan
Duration: 9 Oct 201114 Oct 2011

Conference

Conference2011 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011)
Abbreviated titleCODES+ISSS 2011
CountryTaiwan
CityTaipe
Period9/10/1114/10/11
OtherPart of the Embedded Systems Week 2011.

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