Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends

K.B. Akesson; Po-Chun Huang; F. Clermidy; D. Dutoit; K.G.W. Goossens; Yuan-Hao Chang; Tei-Wei Kuo; P. Vivet; D. Wingard

Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends

K.B. Akesson, Po-Chun Huang, F. Clermidy, D. Dutoit, K.G.W. Goossens, Yuan-Hao Chang, Tei-Wei Kuo, P. Vivet, D. Wingard

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power.

Original language	English
Title of host publication	Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	3-12
ISBN (Print)	978-1-4503-0715-4
Publication status	Published - 2011
Event	2011 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011) - Taipe, Taiwan Duration: 9 Oct 2011 → 14 Oct 2011

Conference

Conference	2011 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011)
Abbreviated title	CODES+ISSS 2011
Country/Territory	Taiwan
City	Taipe
Period	9/10/11 → 14/10/11
Other	Part of the Embedded Systems Week 2011.

Cite this

Akesson, K. B., Huang, P.-C., Clermidy, F., Dutoit, D., Goossens, K. G. W., Chang, Y.-H., Kuo, T.-W., Vivet, P., & Wingard, D. (2011). Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends. In Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan (pp. 3-12). Institute of Electrical and Electronics Engineers.

Akesson, K.B. ; Huang, Po-Chun ; Clermidy, F. et al. / Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends. Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan. Piscataway : Institute of Electrical and Electronics Engineers, 2011. pp. 3-12

@inproceedings{2649c8ce1f7e4d8b94d8152075c0110f,

title = "Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends",

abstract = "Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power.",

author = "K.B. Akesson and Po-Chun Huang and F. Clermidy and D. Dutoit and K.G.W. Goossens and Yuan-Hao Chang and Tei-Wei Kuo and P. Vivet and D. Wingard",

year = "2011",

language = "English",

isbn = "978-1-4503-0715-4",

pages = "3--12",

booktitle = "Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2011 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011), CODES+ISSS 2011 ; Conference date: 09-10-2011 Through 14-10-2011",

}

Akesson, KB, Huang, P-C, Clermidy, F, Dutoit, D, Goossens, KGW, Chang, Y-H, Kuo, T-W, Vivet, P & Wingard, D 2011, Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends. in Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan. Institute of Electrical and Electronics Engineers, Piscataway, pp. 3-12, 2011 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011), Taipe, Taiwan, 9/10/11.

Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends. / Akesson, K.B.; Huang, Po-Chun; Clermidy, F. et al.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan. Piscataway: Institute of Electrical and Electronics Engineers, 2011. p. 3-12.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends

AU - Akesson, K.B.

AU - Huang, Po-Chun

AU - Clermidy, F.

AU - Dutoit, D.

AU - Goossens, K.G.W.

AU - Chang, Yuan-Hao

AU - Kuo, Tei-Wei

AU - Vivet, P.

AU - Wingard, D.

PY - 2011

Y1 - 2011

N2 - Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power.

AB - Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power.

M3 - Conference contribution

SN - 978-1-4503-0715-4

SP - 3

EP - 12

BT - Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2011 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011)

Y2 - 9 October 2011 through 14 October 2011

ER -

Akesson KB, Huang PC, Clermidy F, Dutoit D, Goossens KGW, Chang YH et al. Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends. In Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2011, 9-14 Oktober 2011, Taipei, Taiwan. Piscataway: Institute of Electrical and Electronics Engineers. 2011. p. 3-12

Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends

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