Memory-Centric Accelerator Design for Convolutional Neural Networks

M.C.J. Peemen, A.A.A. Setio, B. Mesman, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

284 Citations (Scopus)
2823 Downloads (Pure)


In the near future, cameras will be used everywhere as flexible sensors for numerous applications. For mobility and privacy reasons, the required image processing should be local on embedded computer platforms with performance requirements and energy constraints. Dedicated acceleration of Convolutional Neural Networks (CNN) can achieve these targets with enough flexibility to perform multiple vision tasks. A challenging problem for the design of efficient accelerators is the limited amount of external memory bandwidth. We show that the effects of the memory bottleneck can be reduced by a flexible memory hierarchy that supports the complex data access patterns in CNN workload. The efficiency of the on-chip memories is maximized by our scheduler that uses tiling to optimize for data locality. Our design flow ensures that on-chip memory size is minimized, which reduces area and energy usage. The design flow is evaluated by a High Level Synthesis implementation on a Virtex 6 FPGA board. Compared to accelerators with standard scratchpad memories the FPGA resources can be reduced up to 13× while maintaining the same performance. Alternatively, when the same amount of FPGA resources is used our accelerators are up to 11× faster.
Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE 31th International Conference on Computer Design (ICCD), 6 - 9 October 2013, Asheville, North Carolina
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4799-2987-0
Publication statusPublished - 2013
Event31st IEEE International Conference on Computer Design (ICCD 2013) - Asheville, NC, United States
Duration: 6 Oct 20139 Oct 2013
Conference number: 31


Conference31st IEEE International Conference on Computer Design (ICCD 2013)
Abbreviated titleICCD 2013
Country/TerritoryUnited States
CityAsheville, NC
Internet address


Dive into the research topics of 'Memory-Centric Accelerator Design for Convolutional Neural Networks'. Together they form a unique fingerprint.

Cite this