Measurement system development and data analysis for ASPIC yield improvement

A. Omar Abdelaziz Ali

    Research output: ThesisEngD Thesis


    Technobis is building a fiber sensing systems based on photonic integrated circuits. We are increasing our production. For this reason, we need to get a stable supply of properly functioning chips. An increase of the production would mean that the price per functioning chip needs to go down. This can be achieved by improving the wafer yield (percentage of working chips per wafer) and by decreasing the testing time per chip. This can be done by:
    • Improving the quality of measurements and the measurement speed at the Technobis facilities.
    • Studying the possibility of performing chip testing at the foundry by the use of built-in test structures on the wafer.
    • Increasing the wafer yield by analysing test data of supplied runs. This data is discussed with the foundry. Using these discussions, SMART Photonics develops a solution to improve the yield. In the next run, it is confirmed whether or not the problem is solved.
    The measurement cycle of the optical chips at Technobis, which includes visual inspection, optical testing and electrical testing, is improved. A manual for visual inspection is made which gives a clear defects overview across the wafer. This overview helped in doing better wafer analysis, understanding the chip defects and it provided the foundry with more information. An overview of the relation of visual defects to actual chip performance has been reported. The measurement setup is improved by installing a new multiprobe system. The new system throughput is increased by a factor 10. This is in line with the current needs of Technobis.
    A test structure is included on the chips to enable doing on-wafer testing at the foundry and to make a first selection of functioning and not functioning chips. This test structure is tested on a design on one of the multi-project wafer runs. Many defects on the chip, such as interrupted waveguides and broken photodiodes, can be detects at the foundry by using this test structure. But further tests for the optical transmission of the chip needs to be done at Technobis.
    Statistical analysis of the most common defects is done. This includes a wafer map per defect. Optical testing and electrical testing for the optical chips are performed. The wafer performance is discussed with SMART Photonics (the wafer supplier) which helped in improving their process. A clear overview on how errors develop from run to run are discussed. This includes the type of the waveguide masks and reactor that are used and changed from run to run. The most occurring errors are disconnected waveguides which results in no optical transmission. A scratch is the second most occurring error. These chips might work as long as the scratch does not interrupted the waveguide completely.
    There were two main issues affecting the chip performance: A high dark current and high waveguide losses. The high dark current of the photodiodes will lead to a high noise level which affects the signal to noise ratio in our sensing system. The dark current values are significantly improved by interrupting the waveguides, which means there are significant electrical connections through the waveguides. This means that the isolation sections are not isolating the photodiodes completely from the waveguides. Increasing the isolation section lengths and/or depths is needed in order to increase the robustness of the design and to re-assure that the resistance of the isolation sections is in-line with the Technobis specifications. The high waveguide losses problems stemmed from Zn diffusion in the waveguides in the old MOVPE (Metalorganic Vapor Phase Epitaxy) reactor. Using a newly calibrated MOVPE reactor has solved this issue. As a consequence, the optical transmission through the chips is increased.
    Using a contact lithography waveguide mask lowered the yield after the first run. This is because a particle or some photoresist sticks to the waveguide mask during contact lithography. Reusing the same mask can cause defects in the next runs. Switching to projection lithography, where no physical contact is made with the mask, is necessary. This adjustment is made in one of the multi-project wafer runs. Based on the visual inspection of samples received from SMART, it was found that using projection lithography to define the waveguides has significantly decreased the number of waveguide defects. This improved the yield. To find the effect of projection lithography on the yield, analysis of a complete wafer run is needed.
    Original languageEnglish
    • Bente, Erwin A.J.M., Supervisor
    • Cottaar, E.J.E. (Ward), Supervisor
    • Docter, V., External supervisor, External person
    • Kat, P., External supervisor, External person
    • Kat, Pim, External supervisor, External person
    Award date28 Mar 2018
    Place of PublicationEindhoven
    Publication statusPublished - 28 Mar 2018

    Bibliographical note

    PDEng thesis.


    Dive into the research topics of 'Measurement system development and data analysis for ASPIC yield improvement'. Together they form a unique fingerprint.

    Cite this