Heterogeneous Multiprocessor systems-on-chip (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet realtime requirements. Designing HMPSoCs with predictable timing behavior is a key challenge, as the current design methods for these platforms are semi-automated, non-predictable, or support limited heterogeneity. In this demonstration, we present a design framework to rapidly generate and implement predictable HMPSoC designs. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints of the application. We also present results of a case study that computes the performance-power tradeoffs of an industrial vision application. A tool-chain targeting the Xilinx Zynq FPGA is also presented.
|Publication status||Published - 1 Jan 2013|
|Event||2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Porto, Portugal|
Duration: 2 Sep 2013 → 4 Sep 2013
|Conference||2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013|
|Period||2/09/13 → 4/09/13|