Lower power by voltage stacking: a fine-grained system design approach

K. Blutman, A. Kapoor, J.G. Martinez, S.H. Fatemi, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)
4 Downloads (Pure)


Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory "on top of it" between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%.

Original languageEnglish
Title of host publicationProceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas
Place of PublicationNew York
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450342360
Publication statusPublished - 5 Jun 2016
Event53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States
Duration: 5 Jun 20169 Jun 2016


Conference53rd Annual ACM IEEE Design Automation Conference, DAC 2016
Country/TerritoryUnited States


  • Charge recycling
  • Level shifter
  • Low power design
  • Microcontroller
  • Stacked circuits
  • Voltage regulator


Dive into the research topics of 'Lower power by voltage stacking: a fine-grained system design approach'. Together they form a unique fingerprint.

Cite this