Lower power by voltage stacking: a fine-grained system design approach

K. Blutman; A. Kapoor; J.G. Martinez; S.H. Fatemi; J. Pineda de Gyvez

doi:10.1145/2897937.2898041

Lower power by voltage stacking: a fine-grained system design approach

K. Blutman, A. Kapoor, J.G. Martinez, S.H. Fatemi, J. Pineda de Gyvez

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

5 Downloads (Pure)

Abstract

Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and V_DD, and the memory "on top of it" between V_DD and 2V_DD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%.

Original language	English
Title of host publication	Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas
Place of Publication	New York
Publisher	Association for Computing Machinery, Inc
Pages	1-5
ISBN (Electronic)	9781450342360
DOIs	https://doi.org/10.1145/2897937.2898041
Publication status	Published - 5 Jun 2016
Event	53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States Duration: 5 Jun 2016 → 9 Jun 2016

Conference

Conference	53rd Annual ACM IEEE Design Automation Conference, DAC 2016
Country/Territory	United States
City	Austin
Period	5/06/16 → 9/06/16

Keywords

Charge recycling
Level shifter
Low power design
Microcontroller
Stacked circuits
Voltage regulator

Access to Document

10.1145/2897937.2898041

Cite this

@inproceedings{f19b2090d004446a90b35d149bcd2468,

title = "Lower power by voltage stacking: a fine-grained system design approach",

abstract = "Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory {"}on top of it{"} between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in {"}stacked mode{"} of 96%.",

keywords = "Charge recycling, Level shifter, Low power design, Microcontroller, Stacked circuits, Voltage regulator",

author = "K. Blutman and A. Kapoor and J.G. Martinez and S.H. Fatemi and {Pineda de Gyvez}, J.",

year = "2016",

month = jun,

day = "5",

doi = "10.1145/2897937.2898041",

language = "English",

pages = "1--5",

booktitle = "Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas",

publisher = "Association for Computing Machinery, Inc",

address = "United States",

note = "53rd Annual ACM IEEE Design Automation Conference, DAC 2016 ; Conference date: 05-06-2016 Through 09-06-2016",

}

Blutman, K, Kapoor, A, Martinez, JG, Fatemi, SH & Pineda de Gyvez, J 2016, Lower power by voltage stacking: a fine-grained system design approach. in Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas., a78, Association for Computing Machinery, Inc, New York, pp. 1-5, 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, Austin, United States, 5/06/16. https://doi.org/10.1145/2897937.2898041

Lower power by voltage stacking: a fine-grained system design approach. / Blutman, K.; Kapoor, A.; Martinez, J.G. et al.
Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas. New York: Association for Computing Machinery, Inc, 2016. p. 1-5 a78.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Lower power by voltage stacking

T2 - 53rd Annual ACM IEEE Design Automation Conference, DAC 2016

AU - Blutman, K.

AU - Kapoor, A.

AU - Martinez, J.G.

AU - Fatemi, S.H.

AU - Pineda de Gyvez, J.

PY - 2016/6/5

Y1 - 2016/6/5

N2 - Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory "on top of it" between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%.

AB - Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory "on top of it" between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%.

KW - Charge recycling

KW - Level shifter

KW - Low power design

KW - Microcontroller

KW - Stacked circuits

KW - Voltage regulator

UR - http://www.scopus.com/inward/record.url?scp=84977151085&partnerID=8YFLogxK

U2 - 10.1145/2897937.2898041

DO - 10.1145/2897937.2898041

M3 - Conference contribution

AN - SCOPUS:84977151085

SP - 1

EP - 5

BT - Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas

PB - Association for Computing Machinery, Inc

CY - New York

Y2 - 5 June 2016 through 9 June 2016

ER -

Lower power by voltage stacking: a fine-grained system design approach

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this