Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices

R. Singanamalla; C. Ravit; G. Vellianitis; J. Petry; V. Paraschiv; J. P. Van Zijl; S. Brus; M. Verheijen; R. G.R. Weemaes; M. Kaiser; J. G.M. Van Berkum; Pascal H.L. Bancken; Rita Vos; H. Yu; K. De Meyer; S. Kubicek; S. Biesemans; J. C. Hooker

doi:10.1109/IEDM.2006.346864

Low V_T Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices

R. Singanamalla
, C. Ravit
, G. Vellianitis
, J. Petry
, V. Paraschiv
, J. P. Van Zijl
, S. Brus
, M. Verheijen
, R. G.R. Weemaes
, M. Kaiser
, J. G.M. Van Berkum
, Pascal H.L. Bancken
, Rita Vos
, H. Yu
, K. De Meyer
, S. Kubicek
, S. Biesemans
, J. C. Hooker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

We report band-edge pFET threshold voltage (V_t ∼ 0.28 V) for MoO_xN_y on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs V_t of 0.45 V using a MoO_x/SiON gate stack, meeting the requirement for 45nm high-V_t CMOS technology. 30 % improvement in performance compared to our base-line Poly-Si/SiON was observed by using both MoO_x/SiON and MoO_x/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO _xN_y gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices.

Original language	English
Title of host publication	2006 International Electron Devices Meeting Technical Digest, IEDM
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	4
ISBN (Print)	1424404398, 9781424404391
DOIs	https://doi.org/10.1109/IEDM.2006.346864
Publication status	Published - 1 Dec 2006
Externally published	Yes
Event	2006 IEEE International Electron Devices Meeting, IEDM 2006 - San Francisco, United States Duration: 10 Dec 2006 → 13 Dec 2006

Conference

Conference	2006 IEEE International Electron Devices Meeting, IEDM 2006
Abbreviated title	IDEM 2006
Country/Territory	United States
City	San Francisco
Period	10/12/06 → 13/12/06

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10.1109/IEDM.2006.346864

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Singanamalla, R., Ravit, C., Vellianitis, G., Petry, J., Paraschiv, V., Van Zijl, J. P., Brus, S., Verheijen, M., Weemaes, R. G. R., Kaiser, M., Van Berkum, J. G. M., Bancken, P. H. L., Vos, R., Yu, H., De Meyer, K., Kubicek, S., Biesemans, S., & Hooker, J. C. (2006). Low V_T Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices. In 2006 International Electron Devices Meeting Technical Digest, IEDM Article 4154283 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/IEDM.2006.346864

@inproceedings{ff020eb2c46b4438af90f11e5e986781,

title = "Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices",

abstract = "We report band-edge pFET threshold voltage (Vt ∼ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoOx/SiON gate stack, meeting the requirement for 45nm high-Vt CMOS technology. 30 \% improvement in performance compared to our base-line Poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO xNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices.",

author = "R. Singanamalla and C. Ravit and G. Vellianitis and J. Petry and V. Paraschiv and \{Van Zijl\}, \{J. P.\} and S. Brus and M. Verheijen and Weemaes, \{R. G.R.\} and M. Kaiser and \{Van Berkum\}, \{J. G.M.\} and Bancken, \{Pascal H.L.\} and Rita Vos and H. Yu and \{De Meyer\}, K. and S. Kubicek and S. Biesemans and Hooker, \{J. C.\}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/IEDM.2006.346864",

language = "English",

isbn = "1424404398",

booktitle = "2006 International Electron Devices Meeting Technical Digest, IEDM",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2006 IEEE International Electron Devices Meeting, IEDM 2006, IDEM 2006 ; Conference date: 10-12-2006 Through 13-12-2006",

}

Singanamalla, R, Ravit, C, Vellianitis, G, Petry, J, Paraschiv, V, Van Zijl, JP, Brus, S, Verheijen, M, Weemaes, RGR, Kaiser, M, Van Berkum, JGM, Bancken, PHL, Vos, R, Yu, H, De Meyer, K, Kubicek, S, Biesemans, S & Hooker, JC 2006, Low V_T Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices. in 2006 International Electron Devices Meeting Technical Digest, IEDM., 4154283, Institute of Electrical and Electronics Engineers, Piscataway, 2006 IEEE International Electron Devices Meeting, IEDM 2006, San Francisco, California, United States, 10/12/06. https://doi.org/10.1109/IEDM.2006.346864

Low V_T Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices. / Singanamalla, R.; Ravit, C.; Vellianitis, G. et al.
2006 International Electron Devices Meeting Technical Digest, IEDM. Piscataway: Institute of Electrical and Electronics Engineers, 2006. 4154283.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices

AU - Singanamalla, R.

AU - Ravit, C.

AU - Vellianitis, G.

AU - Petry, J.

AU - Paraschiv, V.

AU - Van Zijl, J. P.

AU - Brus, S.

AU - Verheijen, M.

AU - Weemaes, R. G.R.

AU - Kaiser, M.

AU - Van Berkum, J. G.M.

AU - Bancken, Pascal H.L.

AU - Vos, Rita

AU - Yu, H.

AU - De Meyer, K.

AU - Kubicek, S.

AU - Biesemans, S.

AU - Hooker, J. C.

PY - 2006/12/1

Y1 - 2006/12/1

N2 - We report band-edge pFET threshold voltage (Vt ∼ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoOx/SiON gate stack, meeting the requirement for 45nm high-Vt CMOS technology. 30 % improvement in performance compared to our base-line Poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO xNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices.

AB - We report band-edge pFET threshold voltage (Vt ∼ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoOx/SiON gate stack, meeting the requirement for 45nm high-Vt CMOS technology. 30 % improvement in performance compared to our base-line Poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO xNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices.

UR - https://www.scopus.com/pages/publications/46049100824

U2 - 10.1109/IEDM.2006.346864

DO - 10.1109/IEDM.2006.346864

M3 - Conference contribution

AN - SCOPUS:46049100824

SN - 1424404398

SN - 9781424404391

BT - 2006 International Electron Devices Meeting Technical Digest, IEDM

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2006 IEEE International Electron Devices Meeting, IEDM 2006

Y2 - 10 December 2006 through 13 December 2006

ER -

Low V_T Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices

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