Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET devices

R. Singanamalla, C. Ravit, G. Vellianitis, J. Petry, V. Paraschiv, J. P. Van Zijl, S. Brus, M. Verheijen, R. G.R. Weemaes, M. Kaiser, J. G.M. Van Berkum, Pascal H.L. Bancken, R. Vos, H. Yu, K. De Meyer, S. Kubicek, S. Biesemans, J. C. Hooker

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

We report band-edge pFET threshold voltage (Vt ∼ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoOx/SiON gate stack, meeting the requirement for 45nm high-Vt CMOS technology. 30 % improvement in performance compared to our base-line Poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO xNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices.

Original languageEnglish
Title of host publication2006 International Electron Devices Meeting Technical Digest, IEDM
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Print)1424404398, 9781424404391
DOIs
Publication statusPublished - 1 Dec 2006
Event2006 IEEE International Electron Devices Meeting (IEDM 2006) - San Francisco, CA, United States
Duration: 10 Dec 200613 Dec 2006

Conference

Conference2006 IEEE International Electron Devices Meeting (IEDM 2006)
Abbreviated titleIDEM 2006
CountryUnited States
CitySan Francisco, CA
Period10/12/0613/12/06

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