Low- voltage folded-switching mixers in 0.18 μm CMOS

V. Vidojkovic, J.D. Tang, van der, A.J. Leeuwenburgh, A.H.M. Roermund, van

Research output: Contribution to journalArticleAcademicpeer-review

198 Citations (Scopus)
139 Downloads (Pure)


Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-µm CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 µm×200 µm. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW
Original languageEnglish
Pages (from-to)1259-1264
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number6
Publication statusPublished - 2005


Dive into the research topics of 'Low- voltage folded-switching mixers in 0.18 μm CMOS'. Together they form a unique fingerprint.

Cite this