Abstract
This paper presents a design of a high-speed, low-voltage, low power consumption comparator with S-R latch for High speed ADC. The comparator is the most important part in the Flash ADC, since the speed and the resolution is determined by the comparator. In this paper, we do the analysis of the traditional comparator and propose a better structure combing sense amplifier and symmetric S-R latch, which can run faster and provide more stable output signal than the traditional structure. The comparator is composed of a latch based amplifier and a S-R latch which provides stable output. There are many issues in the design of the comparator, we will discuss those design issues in this paper.
Original language | English |
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Title of host publication | Conference Proceedings of the International Symposium on Signals, Systems and Electronics |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 126-129 |
Number of pages | 4 |
Volume | 1 |
ISBN (Print) | 9781424463558 |
DOIs | |
Publication status | Published - 2010 |
Event | 2010 International Symposium on Signals, Systems and Electronics (ISSSE 2010), September 17-20, 2010, Nanjing, China - Nanjing, China Duration: 17 Sept 2010 → 20 Sept 2010 |
Conference
Conference | 2010 International Symposium on Signals, Systems and Electronics (ISSSE 2010), September 17-20, 2010, Nanjing, China |
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Country/Territory | China |
City | Nanjing |
Period | 17/09/10 → 20/09/10 |