Low voltage comparator for High speed ADC

Hao Gao, P. Baltus, Qiao Meng

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Abstract

This paper presents a design of a high-speed, low-voltage, low power consumption comparator with S-R latch for High speed ADC. The comparator is the most important part in the Flash ADC, since the speed and the resolution is determined by the comparator. In this paper, we do the analysis of the traditional comparator and propose a better structure combing sense amplifier and symmetric S-R latch, which can run faster and provide more stable output signal than the traditional structure. The comparator is composed of a latch based amplifier and a S-R latch which provides stable output. There are many issues in the design of the comparator, we will discuss those design issues in this paper.

Original languageEnglish
Title of host publicationConference Proceedings of the International Symposium on Signals, Systems and Electronics
PublisherInstitute of Electrical and Electronics Engineers
Pages126-129
Number of pages4
Volume1
ISBN (Print)9781424463558
DOIs
Publication statusPublished - 2010
Event2010 International Symposium on Signals, Systems and Electronics (ISSSE 2010), September 17-20, 2010, Nanjing, China - Nanjing, China
Duration: 17 Sep 201020 Sep 2010

Conference

Conference2010 International Symposium on Signals, Systems and Electronics (ISSSE 2010), September 17-20, 2010, Nanjing, China
CountryChina
CityNanjing
Period17/09/1020/09/10

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Gao, H., Baltus, P., & Meng, Q. (2010). Low voltage comparator for High speed ADC. In Conference Proceedings of the International Symposium on Signals, Systems and Electronics (Vol. 1, pp. 126-129). [5607121] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSSE.2010.5607121