Low-power operation using self-timed circuits and adaptive scaling of the supply voltage

Lars S. Nielsen, Cees Niessen, Jens SparsØ, Kees Van Berkel

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

Abstract

Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may be obtained by combining the self-timed circuits with a mechanism that adaptively adjusts the supply voltage to the smallest possible, while maintaining the performance requirements. This paper describes such a mechanism, analyzes the possible power savings, and presents a demonstrator chip that has been fabricated and tested. The idea of voltage scaling has been used previously in synchronous circuits, and the contributions of the present paper are: 1) the combination of supply scaling and self-timed circuitry which has some unique advantages, and 2) the thorough analysis of the power savings that are possible using this technique.

Original languageEnglish
Title of host publicationLow-Power CMOS Design
EditorsAnantha Chandrakasan, Robert Brodersen
PublisherWiley-IEEE
Pages150-156
Number of pages7
ISBN (Electronic)9780470545058
ISBN (Print)9780780334298
DOIs
Publication statusPublished - 1 Jan 1998
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 1998 the Institute of electrical and electronics engineers, Inc. All rights reserved.

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