Low power Karnaugh map approximate adder for error compensation in loop accumulations

Chunmei Yang, Hailong Jiao

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Approximate computing has recently emerged as a promising paradigm to achieve considerable energy savings at the expense of degraded computing accuracy. In this paper, an approximate adder is proposed to reduce the power consumption while providing minimal computation errors for loop accumulation, which is a crucial operation in various signal processing algorithms. The proposed adder is based on smart modification of Karnaugh map to generate compensation effect with loop accumulation. With the proposed approximate adder, the power consumption is reduced by up to 42.8% and 24.9% compared to fully-accurate adder and the previously published approximate adders, respectively, in an industrial 65-nm CMOS technology. Furthermore, the computation accuracy is enhanced by up to 31x with the proposed approximate adder compared with the previously published approximate adders. Using the product of normalized mean error distance (NMED) and power consumption as the Figure-of-Merit (FoM), the proposed approximate adder improves the FoM by up to 37.7x compared to the previously published approximate adders.

Original languageEnglish
Title of host publication17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)978-1-7281-1853-6
DOIs
Publication statusPublished - 1 Jun 2019
Event17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Suzhou, China
Duration: 17 Jun 201919 Jun 2019

Conference

Conference17th IEEE International Conference on IC Design and Technology, ICICDT 2019
CountryChina
CitySuzhou
Period17/06/1919/06/19

Fingerprint

Error compensation
Adders
Electric power utilization
Energy conservation
Signal processing

Keywords

  • computation accuracy
  • digital signal processing
  • error compensation
  • Karnaugh map
  • loop accumulation

Cite this

Yang, C., & Jiao, H. (2019). Low power Karnaugh map approximate adder for error compensation in loop accumulations. In 17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings [8790952] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICICDT.2019.8790952
Yang, Chunmei ; Jiao, Hailong. / Low power Karnaugh map approximate adder for error compensation in loop accumulations. 17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2019.
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Yang, C & Jiao, H 2019, Low power Karnaugh map approximate adder for error compensation in loop accumulations. in 17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings., 8790952, Institute of Electrical and Electronics Engineers, Piscataway, 17th IEEE International Conference on IC Design and Technology, ICICDT 2019, Suzhou, China, 17/06/19. https://doi.org/10.1109/ICICDT.2019.8790952

Low power Karnaugh map approximate adder for error compensation in loop accumulations. / Yang, Chunmei; Jiao, Hailong.

17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2019. 8790952.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Yang C, Jiao H. Low power Karnaugh map approximate adder for error compensation in loop accumulations. In 17th IEEE International Conference on IC Design and Technology, ICICDT 2019 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers. 2019. 8790952 https://doi.org/10.1109/ICICDT.2019.8790952