Low-power die-level process variation and temperature monitors for yield analysis and optimization in deep-submicron CMOS.

A. Zjajo, M.J. Barragan, J. Pineda de Gyvez

Research output: Contribution to journalArticleAcademicpeer-review

10 Citations (Scopus)

Abstract

This paper reports design, efficiency, and measurement results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation-maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-to-digital converter fabricated in standard single poly six-metal 90-nm CMOS.
Original languageEnglish
Pages (from-to)2212-2221
Number of pages10
JournalIEEE Transactions on Instrumentation and Measurement
Volume61
Issue number8
DOIs
Publication statusPublished - 2012

Fingerprint

Dive into the research topics of 'Low-power die-level process variation and temperature monitors for yield analysis and optimization in deep-submicron CMOS.'. Together they form a unique fingerprint.

Cite this