Low Power Coarse-Grained Reconfigurable Instruction Set Processor.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Proc. of the 13th International Conference on Field Programmable Logic and Applications (FPL 2003)
Pages	230-239
Publication status	Published - 2003
Event	conference; FPL 2003, Lisbon, Portugal; 2003-09-01; 2003-09-03 - Duration: 1 Sept 2003 → 3 Sept 2003

Conference	conference; FPL 2003, Lisbon, Portugal; 2003-09-01; 2003-09-03
Period	1/09/03 → 3/09/03
Other	FPL 2003, Lisbon, Portugal

Cite this

@inproceedings{2e416b3565584bc0935157acd3300b3e,

title = "Low Power Coarse-Grained Reconfigurable Instruction Set Processor.",

author = "F. Barat and M. Jayapala and \{Aa, van der\}, T. and G. Deconinck and R. Lauwereins and H. Corporaal",

year = "2003",

language = "English",

isbn = "3-549-40822-3",

pages = "230--239",

booktitle = "Proc. of the 13th International Conference on Field Programmable Logic and Applications (FPL 2003)",

note = "conference; FPL 2003, Lisbon, Portugal; 2003-09-01; 2003-09-03 ; Conference date: 01-09-2003 Through 03-09-2003",

}

TY - GEN

T1 - Low Power Coarse-Grained Reconfigurable Instruction Set Processor.

AU - Barat, F.

AU - Jayapala, M.

AU - Aa, van der, T.

AU - Deconinck, G.

AU - Lauwereins, R.

AU - Corporaal, H.

PY - 2003

Y1 - 2003

M3 - Conference contribution

SN - 3-549-40822-3

SP - 230

EP - 239

BT - Proc. of the 13th International Conference on Field Programmable Logic and Applications (FPL 2003)

T2 - conference; FPL 2003, Lisbon, Portugal; 2003-09-01; 2003-09-03

Y2 - 1 September 2003 through 3 September 2003

ER -