Low power and robust memory circuits with asymmetrical ground gating

Hailong Jiao, Yongmin Qiu, V. Kursun

Research output: Contribution to journalArticleAcademicpeer-review

31 Citations (Scopus)
1 Downloads (Pure)


Multi-threshold CMOS (MTCMOS) technique is commonly used for suppressing leakage currents in idle circuits. The application of MTCMOS technique to static random access memory (SRAM) circuits is investigated in this paper. Two asymmetrically ground-gated MTCMOS SRAM circuits are presented for providing a low-leakage SLEEP mode with data retention capability. The read and hold static noise margins are increased by up to 7.24× and 2.39×, respectively, with the new asymmetrical SRAM cells as compared to conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. The overall electrical quality of a memory array is enhanced by up to 103.52× and 57.75% with the proposed asymmetrically ground-gated memory cells as compared to the conventional ground-gated 6T and eight-transistor (8T) SRAM cells, respectively. The new asymmetrical SRAM cells also exhibit enhanced tolerance to process parameter variations and lower minimum applicable power supply voltages as compared with the conventional 6T and 8T SRAM cells.

Original languageEnglish
Pages (from-to)109-119
Number of pages11
JournalMicroelectronics Journal
Publication statusPublished - 1 Feb 2016


  • Data retention SLEEP mode
  • Data stability
  • Leakage power consumption
  • Minimum power supply voltage
  • Process parameter variations
  • Static noise margin
  • Write assist transistor
  • Write voltage margin


Dive into the research topics of 'Low power and robust memory circuits with asymmetrical ground gating'. Together they form a unique fingerprint.

Cite this