Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

Y. Sun; H. Jiao; V. Kursun

doi:10.1109/ICM.2014.7071832

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

Y. Sun, H. Jiao, V. Kursun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.

Original language	English
Title of host publication	Proceedings of the 26th IEEE International Conference on Microelectronics (ICM 2014), 14-17 December 2014, Doha, Quatar
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	164-167
ISBN (Electronic)	978-1-4799-8153-3
ISBN (Print)	978-1-4799-8154-0
DOIs	https://doi.org/10.1109/ICM.2014.7071832
Publication status	Published - 2014
Event	conference; IEEE International Conference on Microelectronics - Duration: 1 Jan 2014 → …

Conference

Conference	conference; IEEE International Conference on Microelectronics
Period	1/01/14 → …
Other	IEEE International Conference on Microelectronics

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10.1109/ICM.2014.7071832

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@inproceedings{0c7d1aafaaf74a63b35430682f083084,

title = "Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins",

abstract = "A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09\% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18\% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.",

author = "Y. Sun and H. Jiao and V. Kursun",

year = "2014",

doi = "10.1109/ICM.2014.7071832",

language = "English",

isbn = "978-1-4799-8154-0",

pages = "164--167",

booktitle = "Proceedings of the 26th IEEE International Conference on Microelectronics (ICM 2014), 14-17 December 2014, Doha, Quatar",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "conference; IEEE International Conference on Microelectronics ; Conference date: 01-01-2014",

}

Sun, Y , Jiao, H & Kursun, V 2014, Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins. in Proceedings of the 26th IEEE International Conference on Microelectronics (ICM 2014), 14-17 December 2014, Doha, Quatar. Institute of Electrical and Electronics Engineers, Piscataway, pp. 164-167, conference; IEEE International Conference on Microelectronics, 1/01/14. https://doi.org/10.1109/ICM.2014.7071832

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins. / Sun, Y.; Jiao, H.; Kursun, V.
Proceedings of the 26th IEEE International Conference on Microelectronics (ICM 2014), 14-17 December 2014, Doha, Quatar. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 164-167.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

AU - Sun, Y.

AU - Jiao, H.

AU - Kursun, V.

PY - 2014

Y1 - 2014

N2 - A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.

AB - A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.

U2 - 10.1109/ICM.2014.7071832

DO - 10.1109/ICM.2014.7071832

M3 - Conference contribution

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BT - Proceedings of the 26th IEEE International Conference on Microelectronics (ICM 2014), 14-17 December 2014, Doha, Quatar

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - conference; IEEE International Conference on Microelectronics

Y2 - 1 January 2014

ER -

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

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