Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

Y. Sun, H. Jiao, V. Kursun

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.
Original languageEnglish
Title of host publicationProceedings of the 26th IEEE International Conference on Microelectronics (ICM 2014), 14-17 December 2014, Doha, Quatar
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages164-167
ISBN (Electronic)978-1-4799-8153-3
ISBN (Print)978-1-4799-8154-0
DOIs
Publication statusPublished - 2014
Eventconference; IEEE International Conference on Microelectronics -
Duration: 1 Jan 2014 → …

Conference

Conferenceconference; IEEE International Conference on Microelectronics
Period1/01/14 → …
OtherIEEE International Conference on Microelectronics

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