Abstract
Digital image processing (DIP) algorithms used in consumer electronics products have high computational complexities. Therefore, in this paper, we propose a novel low complexity 2D adaptive DIP algorithm. The proposed algorithm reduces computational complexities of 2D DIP algorithms by exploiting pixel correlations in input image without reducing quality of output image. We also designed a low energy 2D adaptive DIP hardware implementing the proposed algorithm. The proposed hardware is verified to work correctly on an FPGA board. It has significantly less energy consumption than original 2D DIP hardware. Therefore, it can be used especially in portable consumer electronics products.
| Original language | English |
|---|---|
| Article number | 8103376 |
| Pages (from-to) | 277-284 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Consumer Electronics |
| Volume | 63 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - Aug 2017 |
| Externally published | Yes |
Funding
Manuscript received July 8, 2017; accepted August 30, 2017. Date of publication September 5, 2017. This research was supported in part by the Scientific and Technological Research Council of Turkey (TUBITAK). (Corresponding author: I. Hamzaoglu.) E. Kalali, I. Hamzaoglu are with Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey (e-mail: {ercankalali, hamzaoglu}@sabanciuniv.edu).
Keywords
- FPGA
- Gaussian Blur
- Hardware Implementation
- Image Sharpening
- Low Energy
- Median Filter
