Loop overhead reduction techniques for coarse grained reconfigurable architectures

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Due to their flexibility and high performance, Coarse Grained Reconfigurable Array (CGRA) are a topic of increasing research interest. However, CGRAs also have the potential to achieve very high energy efficiency in comparison to other reconfigurable architectures when hardware optimizations are applied. Some of these optimizations are common for more traditional processors but can also lead to large efficiency gains for reconfigurable architectures. This paper investigates three hardware based loop optimization techniques that can significantly improve the energy efficiency of CGRAs. The three techniques are evaluated on processing kernels from the image processing domain as well as an industrial computer vision application. Energy consumption and area estimates are obtained using a CGRA synthesized with a commercial 40nm library. For the three applied techniques (zero-overhead loop accelerator, single-cycle loop support, and loop buffers) the simulation results show overall energy gains of 6.8% for zero-overhead loop support, 13.2% for ZOLA combined with single-cycle loop support and 18.3% for a combination of all optimizations.
Original languageEnglish
Title of host publicationDSD 2017 - 20th Euromicro Conference on Digital System Design, 30 August - 1 September 2017, Vienna, Austriavadivel wijtvliet jordfans
EditorsMartin Novotny, Hana Kubatova, Amund Skavhaug
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages8
ISBN (Electronic)978-1-5386-2146-2
ISBN (Print)978-1-5386-2147-9
Publication statusPublished - 28 Sept 2017


  • CGRA
  • energy efficiency
  • loop support
  • reconfigurable architectures


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