Abstract
Memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.
| Original language | English |
|---|---|
| Patent number | WO2012119988 |
| IPC | G11C 11/ 419 A I |
| Priority date | 4/03/11 |
| Publication status | Published - 13 Sept 2012 |
| Externally published | Yes |
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