Abstract
According to the general concept disclosed herein, a circuit for adaptive matching of a load impedance to a predetermined load-line impedance of a load-line connected to a power amplifier output includes a fixed matching network between the power transistor and an adaptive matching network, whereby the fixed matching network acts as an impedance inverter which results in a relatively low insertion loss at high power. Results indicate that the impedance-inverting network can be used over more than a factor of 10 in impedance variation. Further, the usage of the fixed matching network, close to the power transistor, allows for the implementation of transmission zeros and/or for a well defined load impedance at a predetermined harmonic frequency, independent of the (variable) load impedance at the fundamental frequency.
| Original language | English |
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| Patent number | US20090174496 |
| Publication status | Published - 9 Jul 2009 |