Limits to performance spread tuning using adaptive voltage and body biasing

M. Meijer; F. Pessolano; J. Pineda de Gyvez

doi:10.1109/ISCAS.2005.1464510

Limits to performance spread tuning using adaptive voltage and body biasing

M. Meijer, F. Pessolano, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

189 Downloads (Pure)

Abstract

We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4× power savings by 6.1× frequency downscaling using AVS, ±24% power and ±22% frequency tuning at nominal conditions using ABB only, 127× power savings with 37.4× frequency downscaling by combining AVS and ABB.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems (ISCAS 2005), 23 - 26 May 2005, Kobe, Japan
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	5-8
Volume	1
ISBN (Print)	0-7803-8834-8
DOIs	https://doi.org/10.1109/ISCAS.2005.1464510
Publication status	Published - 2005
Externally published	Yes

Access to Document

10.1109/ISCAS.2005.1464510

Metis247716Final published version, 409 KB

Cite this

@inproceedings{57a91557ce87457fa3c76666f19b701d,

title = "Limits to performance spread tuning using adaptive voltage and body biasing",

abstract = "We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4× power savings by 6.1× frequency downscaling using AVS, ±24% power and ±22% frequency tuning at nominal conditions using ABB only, 127× power savings with 37.4× frequency downscaling by combining AVS and ABB.",

author = "M. Meijer and F. Pessolano and {Pineda de Gyvez}, J.",

year = "2005",

doi = "10.1109/ISCAS.2005.1464510",

language = "English",

isbn = "0-7803-8834-8",

volume = "1",

pages = "5--8",

booktitle = "IEEE International Symposium on Circuits and Systems (ISCAS 2005), 23 - 26 May 2005, Kobe, Japan",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Limits to performance spread tuning using adaptive voltage and body biasing. / Meijer, M.; Pessolano, F.; Pineda de Gyvez, J.
IEEE International Symposium on Circuits and Systems (ISCAS 2005), 23 - 26 May 2005, Kobe, Japan. Vol. 1 Piscataway: Institute of Electrical and Electronics Engineers, 2005. p. 5-8.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Limits to performance spread tuning using adaptive voltage and body biasing

AU - Meijer, M.

AU - Pessolano, F.

AU - Pineda de Gyvez, J.

PY - 2005

Y1 - 2005

N2 - We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4× power savings by 6.1× frequency downscaling using AVS, ±24% power and ±22% frequency tuning at nominal conditions using ABB only, 127× power savings with 37.4× frequency downscaling by combining AVS and ABB.

AB - We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4× power savings by 6.1× frequency downscaling using AVS, ±24% power and ±22% frequency tuning at nominal conditions using ABB only, 127× power savings with 37.4× frequency downscaling by combining AVS and ABB.

U2 - 10.1109/ISCAS.2005.1464510

DO - 10.1109/ISCAS.2005.1464510

M3 - Conference contribution

SN - 0-7803-8834-8

VL - 1

SP - 5

EP - 8

BT - IEEE International Symposium on Circuits and Systems (ISCAS 2005), 23 - 26 May 2005, Kobe, Japan

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Limits to performance spread tuning using adaptive voltage and body biasing

Abstract

Access to Document

Fingerprint

Cite this