Limit cycle counting based smart background calibration of continuous time sigma delta ADCs

In this paper, a new background calibration technique for sigma delta modulators (SDMs) is presented. This method uses limit cycle analysis of SDMs as a theoretical base. Several non-idealities such as loop filter inaccuracy, excess loop delay and instability can be corrected using this technique. This method works in background by observing the bit-stream and generating limit cycle distributions during normal operation. It then uses the distribution data to estimate the non-idealities and takes steps to correct them. As a result, the proposed technique does not require any special test signals or customized hardware circuitry used in other calibration approaches. This technique can be used to calibrate the loop filter coefficients, delay and even hysteresis in the quantizer to obtain the required performance.