Abstract
In this paper, the authors extend their work on the balancing-based subthreshold cell sizing methodology. The libraries were benchmarked against a library tuned for super-threshold operation. Two sets of standard cells have been properly sized for operation at 0.3V, and further characterized at different voltages. A super-threshold 90 nm low power library was chosen as a reference library to compare timing, power and voltage scaling ability. The resented libraries show a 31% timing improvement at 0.3 V without area penalty over the conventional library. The comparison of libraries at different voltages shows that with respect to the super-threshold library, the presented library with only transistor channel width tuning has on average 10% better timing from 0.3 V to 1.2 V, and that this library with both transistor channel width and length tuning show timing improvements of 31.4% and 6.9% when the supply voltage increases from 0.3 V to 0.6 V, respectively
Original language | English |
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Title of host publication | Proceedings of the 2012 IEEE Subthreshould Microelectronics Conference (SubVT 2012), October 09-10, 2012, Waltham, Massachussetts |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 1-3 |
ISBN (Print) | 978-1-4673-1586-9 |
DOIs | |
Publication status | Published - 2012 |