Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture

M.A. Perkowski; D. Foote; Qihong Chen; A. Al-Rabadi; L. Jozwiak

doi:10.1109/MM.2002.1013304

Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture

M.A. Perkowski
, D. Foote
, Qihong Chen
, A. Al-Rabadi
, L. Jozwiak

Research output: Contribution to journal › Article › Academic › peer-review

6 Citations (Scopus)

1 Downloads (Pure)

Abstract

For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation

Original language	English
Pages (from-to)	52-61
Number of pages	10
Journal	IEEE Micro
Volume	22
Issue number	3
DOIs	https://doi.org/10.1109/MM.2002.1013304
Publication status	Published - 2002

Access to Document

10.1109/MM.2002.1013304

Cite this

@article{ecaea9e29795477e9868122ab6aa719c,

title = "Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture",

abstract = "For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation",

author = "M.A. Perkowski and D. Foote and Qihong Chen and A. Al-Rabadi and L. Jozwiak",

year = "2002",

doi = "10.1109/MM.2002.1013304",

language = "English",

volume = "22",

pages = "52--61",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "3",

}

TY - JOUR

T1 - Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture

AU - Perkowski, M.A.

AU - Foote, D.

AU - Chen, Qihong

AU - Al-Rabadi, A.

AU - Jozwiak, L.

PY - 2002

Y1 - 2002

N2 - For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation

AB - For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation

U2 - 10.1109/MM.2002.1013304

DO - 10.1109/MM.2002.1013304

M3 - Article

SN - 0272-1732

VL - 22

SP - 52

EP - 61

JO - IEEE Micro

JF - IEEE Micro

IS - 3

ER -

Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture

Abstract

Access to Document

Fingerprint

Cite this