Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture

M.A. Perkowski, D. Foote, Qihong Chen, A. Al-Rabadi, L. Jozwiak

    Research output: Contribution to journalArticleAcademicpeer-review

    4 Citations (Scopus)
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    Abstract

    For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation
    Original languageEnglish
    Pages (from-to)52-61
    Number of pages10
    JournalIEEE Micro : Chips, Systems, Software and Applications
    Volume22
    Issue number3
    DOIs
    Publication statusPublished - 2002

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